01007nam a22002535 4500 1/23257 040524s2003 us a 001 0 eng 1402076525 24794 DLC GR-PeUP 621.39'5 RAD Radecka, Katarzyna. Verification by error modeling : using testing techniques in hardware verification / Radecka Katarzyna, Zilic, Zeljko. Boston : Kluwer Academic, 2003. xiv, 216 p. : ill. ; 25 cm. Frontiers in electronic testing ; Includes bibliographical references and index. Integrated circuits Very large scale integration Computer-aided design. Integrated circuits Verification. Error analysis (Mathematics) Zilic, Zeljko. Frontiers in electronic testing ; 25 INST UNIPILB MAIN 20040915 621.39'5 RAD 00143843 00143843 LOAN 0 1 /webopac/covers/02/24794_1402076525.jpg