00954nam a22002295 4500 1/23246 040524s1998 enka 001 0 eng 9780792381846 24783 DLC GR-PeUP 621.3815 HUA Huang, Shi-Yu , 1965- Formal equivalence checking and design debugging / by Shi-Yu Huang and Kwang-Ting (Tim) Cheng Boston : Kluwer Academic Publishers, 1998 xviii, 229 σ. εικ.; 24 εκ. Περιλαμβάνει βιβλιογραφία και ευρετήριο Integrated circuits Verification. Electronic circuit design Data processing. Application specific integrated circuits Design and construction. Cheng, Kwang-Ting 1961- INST UNIPILB MAIN 20040913 621.3815 HUA 00143821 00143821 LOAN 0 1 /webopac/covers/02/24783_9780792381846.jpg